differential pecl series differential pecl output, some with enable/ disable function standard specifications overall frequency stability operating temperature range 0 to +80 c is standard, but can be extended to storage temperature range - 55 to +125 c - 40 to +85 c mechanical: see next pages supply voltage (vcc) 3.3 volts 5 % standard, but 5.0 volts or 2.5 volts also available. see t est cirucit 5. e/d internal pullup 50 kohm minimum to vcc all other models output enable/disable (e/d) output enable time output disable time when disabled output symmetry 45/55% referenced to 50% of amplitude output rise & fall (tr & tf) 1.0 ns maximum when vth is 10% and 90% of waveform < 250 mhz = 90 ma maximum, 250 mhz and above = 100 ma maximu m supply current (icc) 2.275 v minimum referenced to ground, vcc = 3.300v, 0.975 v minimum referenced to termination voltage, - 1.025 v minimum referenced to vcc output high level 1.680 v maximum referenced to ground, vcc = 3.300v, 0.380 v maximum referenced to termination voltage, - 1.620 v maximum referenced to vcc output low level 1 ps rms maximum measured from 12 khz to 20 mhz from fnominal jitter v enable 0.7 vcc minumum referenced to ground 0.3 vcc maximum referenced to ground v disable (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 1 pl tronics, inc. 100 ns maximum 100 ns maximum output disable time q output = logic low, qn output = logic high. both outputs a re active pe7745d only output enable / disable 50 ppm, 25 ppm, 20 ppm over operating temperature range available in 9 different package/configurations, see next pa ges d package j package replacement b package m package note 1: pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . pecl, lvds, ocxo page 1 - 7 mar 2004 pecl and ecl are identical circuits. ecl has the most positive pin as ground and is ideally termi nated by 50 ohms to - 2.00 v pecl has the most negative pin as ground and is ideally term inated by 50 ohms to the most (positive voltage less 2.00 v) output enable time 200 ns maximum at output enable or 1 ms maximum at output en abled and stable high level input current low level input current -20 ua maximum at enable / disable pin = 0.7 vcc -200 ua maximum at enable / disable pin = 0 v 200 ns maximum at output disable output disable time vcc supply current disabled < 1 ma. both outputs are high im pedance when disabled.
mechanical: not to scale solder pads inches (mm) mar 2004 due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an inte rnal code. (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 2a pl tronics, inc. 6 pad 'b pkg' pecl series differential pecl output with enable/ disable function 10.00 mhz ? 650.00 mhz 6 pad 14x10x3mm leadless surface mount clock oscillator pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . consult factory for available frequencies and specs. not all options available for all frequencies. a special part numbe r may be assigned. part numbering guide frequency stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration a nd load packaging tube or 24mm tape, 16mm pitch portions of the part number that appear after the frequency may not be marked on part (c of c provided) 0.055 (1.4) 0.200 (5.08) 1 3 4 2 5 6 0.228 (5.8) 0.118 (3.0) 0 .145 (3.68) 0.400 (10.16) max 0.560 (14.23) max 0.125 (3.17) max 0.200 (5.08) 1 2 3 4 5 6 pin signal 1 n.c. 2 e/d 3 gnd 4 q out 5 qn out 6 vcc 1 n.c. 2 e/d 3 gnd 4 q out 5 qn out 6 vcc pin signal 1 e/d 2 n.c. 3 gnd 4 q out 5 qn out 6 vcc pin signal 1 qn out 2 e/d 3 gnd 4 q out 5 n.c. 6 vcc pin signal pe1145t pe1145b pe3345b pe3 745b model series frequency stability 45 = 50 ppm 44 = 25 ppm frequency in mhz special specifications (choose all that apply) e: extended operating temperature range (- 40 to +85 c) f: 47.5 /52.5% symmetry at 50% of vcc v: supply voltage of 3.3 volts 10% w: supply voltage of 2.5 volts 5 % y: supply voltage of 5.0 volts 10% pe11 45 b v - 70.0m - xxx (internal code or blank) 20 = 20 ppm pe1145b = e/d on pin2, qn on pin 1 pe3345b = e/d on pin 2, qn on pin 5 pe3745b = e/d on pin 1, qn on pin 5 10.0 mhz to 170 mhz pe1145t = e/d on pin2 110.0 mhz to 650 mhz 10.0 mhz to 170.0 mhz 110.0 mhz to 650.0 mhz pe1145t, pe1145b, pe3345b, pe3745b see page 6 for layout guidelines pecl, lvds, ocxo page 1 - 7
mar 2004 (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 6 pl tronics, inc. pecl and lvds layout guidelines pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . top side bypass bottom side bypass multi layer bypass 0.055 (1.4) 0.100 (2.54) 0.200 (5.08) 0 .185 (4.7) 0 .087 (2.2) solder pad layout which accommodates all pecl surface mount devices 'b pkg' 5 x7 suggested pcb layouts the output line should be designed with proper characteristi c impedance. pletronics recommends laying out for the larger 'b package' with pads long enough to accept the smaller 5 x 7mm device. this permits the best option for alternate sources of device. pletronics also recommends connecting pin 1 and pin 2 together on the models with q & qn out on pins 4 & 5. this allows having e/d on either pin 1 or pin 2. for optimum jitter performance, pletronics recommends: a ground plane under the device with any other signals below the ground plane minimize other rf signals near device no large transient signals (both current and voltage) should be routed under the device do not layout near a large magnetic field such as a high fre quency switching power supply do not place near piezoelectric buzzers or mechancial fans 250 200 150 100 50 seconds 215 c 10 c 10 seconds max 260 c max 120 to 160 seconds 175 c 10 c t rise= 4 degree/second max temperature c reflow cycle for lead free processing pecl, lvds, ocxo page 1 - 7
mar 2004 (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 6a pl tronics, inc. pecl and lvds layout guidelines continued pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . vcc vcc - 2.00 v gnd out vcc oscillator vcc gnd out vcc oscillator pecl terminations: lvds terminations: mixed system power supply: 50 ohm vcc gnd out vcc oscillator r load vcc gnd q out qn out vcc oscillator 100 ohm r1 r2 suggested terminations for 50 ohm impedance matched terminat ion simple termination for non impedance matched termination vcc 5.0 v 3.3 v 2.5 v r1 82 ohm 130 ohm 249 ohm vcc 5.0 v 3.3 v 2.5 v r load 274 ohm 147 ohm 86.6 ohm r2 130 ohm 82 ohm 61.9 ohm thevenin equivalent termination design pcb traces for 50 ohm characteristic impedance to use multiple supply voltages requires level translation. direct circuit connection is not valid. mixed supply voltages are allowed. no translation is necessa ry. (ecl is returned to the most positive supply and this is common to all circuits) mixed supply voltages are allowed. lvds signal levels are po wer supply independent. 3.3 v lvds oscillators properly interface 2.5 v logic arrays for example. pecl ecl lvds
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